1. Field of the Invention
This invention relates to a data processing device with a test circuit with which the test vectors of a scan test for functional elements such as a plurality of macro blocks connected to a common bus can be generated very efficiently.
2. Description of the Prior Art
Functional elements (hereinafter referred to as macro blocks) each including an adder, an arithmetic and logic calculation unit, a random access memory (RAM), and a read only memory (ROM), and others combinational circuits or sequential circuits are connected to an address bus or a data bus to transfer data stored in the macro blocks in a data processing device, such as a microprocessor.
In general, there are two types of data transfer control methods for the microprocessor. The first method, for example, is executed by using a microprogram. In the first method, input/output operation for data is performed through a common bus under the control of one control block. In the second method, the data input-output operation is controlled through the common bus under the control of plural control blocks. Both the first and second methods are commonly used in conventional microprocessor devices including large scale, complicated and integrated circuits.
In these conventional microprocessor devices, only one macro block is selected for the data output operation through a common bus to prohibit the data output operation by other macro blocks.
The control operation for the data input/output operation, as described above, is used in a conventional microprocessor device to avoid conflict between data provided by the two or more macro blocks on the common bus (bus data conflict).
It is almost impossible, to thoroughly test conventional microprocessor device using the second method in the normal operation mode, using only test instructions and data provided from outside the microprocessor device. This is because the microprocessor device includes a great number of functional elements and the control operations among the functional elements are much more complicated than in the first data transfer control method. Normal operation mode, as used herein, means that mode in which a microprocessor device operates to execute its normal functions.
As a solution for the above problem, in general, a scan design method has been adopted to test the dominant part of the microprocessor device. The main point of that scan design method is that, the flip-flop (F/Fs) of the functional elements, the macro blocks and the like, and an input terminal and an output terminal of the microprocessor device, are connected in series and operate as if each of them are a part of a shift register directly connected to the outside the device in a `scan` operation mode.
In more detail, a scan test (operation) with a test vector in the scan design method is carried out as follows:
(1) a test vector is set in series from the outside of the device through the chain of F/Fs in the scan operation mode,
(2) one cycle of the test operations of the functional elements, the macro blocks and the like, is carried out in the normal operation mode, and
(3) resultant test data stored in the F/Fs is read out to the outside of the device again in the scan operation mode.
As explained above, in the scan operation mode based on the scan design method, the test vectors and the resultant test data are transferred in series into the F/Fs and out of the F/Fs, respectively.
As a result, though test operations for the sequential circuits incorporated in the microprocessor device are correctly executed by using the scan design method, the test operations take much time.
In the prior art, a special test method other than the scan design method is therefore utilized for testing operations of macro blocks such as ROM, RAM and other memory devices. This reduces the test time required for testing operation of the devices in the conventional microprocessors.
The scan design method is used for a macro block, such as a control logic ,unit and other kinds of the macro blocks, which are mainly composed of random logic circuits and F/Fs.
The data output control operation for a data processing device in which a scan test (in which a test vector is set in the device by the scan operation based on the scan design method, the test operation for the device is carried out, and then resultant test data is read out to the outside of the device) can be carried out using the scan design method, is explained with reference to FIG. 1.
The scan test for the functional blocks can be executed by the data output operation based on the scan design method.
FIG. 1 is a block diagram showing the configuration of the main part of the data processing device in which the scan test operation can be executed. In the same diagram, outputs of the macro blocks 1a and 1b are transferred alternately into a common bus 4 through a pair of bus buffers 3a and 3b under the control of a bus control circuit 2. The bus control circuit 2 includes a random logic circuit and, in some cases, a micro instruction control circuit and the like. One of the bus buffers 3a and 3b is selected by the bus control circuit 2. The functional blocks 1a and 1b may have data input paths from the common bus 4, which are depicted as paths 50a and 50b, respectively.
In the scan test, for example, the test vectors, which are generated automatically by a Computer Aided Testing (CAT) system based on the D-algorithm, are provided to the macro blocks 1a and 1b, and the bus control circuit 2 in the scan operation mode. Next, only one cycle of the normal operation of the data processing device is executed, then the resultant test data of the execution are stored temporarily in a resister 5, which is connected to the common bus 4, or registers in the macro blocks 1a and 1b (not shown).
The resultant test data are read out in series through the resister 5 or the registers in the macro blocks 1a and 1b, and through an output terminal to the outside of the device in the scan operation mode.
Four cases for controlling output operations from the macro blocks 1a and 1b to the common bus 4 through the bus buffers 3a and 3b by the bus control circuit 2 in the scan test operation, are as follows:
(1) the output from the macro block 1a is transferred to the common bus 4 through the bus buffer 3a, which is only in the active state under the control of the bus control circuit 2,
(2) the output from the macro block 1b is transferred to the common bus 4 through the bus buffer 3b, which is only in the active state under the control of the bus control circuit 2.
(3) the outputs from the macro blocks 1a and 1b cannot be transferred to the common bus 4 through the bus buffers 3a and 3b, both of which are in the inactive state under the control of the bus control circuit 2, and
(4) the outputs from the macro blocks 1a and 1b are transferred to the common bus 4 through the bus buffers 3a and 3b, both of which are in the active state under the control of the bus control circuit 2.
In general, the frequency at which each of the four states described above is generated by an automatic test vector generator is approximately equal in the scan test operation in the conventional data processing device.
There is no advantage in executing the scan test operations under the two states (3) and (4), because no outputs obtained from the macro blocks 1a and 1b are transferred to the common bus 4 in the state (3). In the state (4), the outputs from the macro blocks 1a and 1b will conflict on the common bus 4. Accordingly, test vectors with the states (3) and (4) have to be excluded from a set of test vectors giving useful information on the faults of the device.
As shown in FIG. 1, in the case where there are two macro blocks which output to the common bus 4, there are the four states for transferring the outputs of the macro blocks under the control of the bus control circuit 2.
The frequency that each state (1), (2), (3), or (4) is generated in automatic test vector generation is nearly the same, so that test vectors giving resultant test data can be obtained only twice in the meaningful generation of the four test vectors with the four states (1), (2), (3), or (4).
In general, test vectors giving meaningful results in the scan test operation can be obtained at a rate of N times in 2.sup.N time scan test vector generation, when the N (N is an integer) macro blocks are connected to the common bus. Therefore the occurrence probability of useful test vectors obtained in the automatic scan test vector generation for the conventional data processing device in which the N of 2.sup.N is two or more is lower than 1.
The greater the number of the macro blocks, the more time it takes to generate useful scan test vectors applicable to the device.
In the prior art, checking operations for detecting whether or not generated test vectors cause data conflict or hi-impedance on a common bus are necessary, in order to obtain useful test vectors after test vectors are generated by the CAT. When these undesirable states occur, the corresponding test vectors are excluded from a set of test vectors applied to the device.
Thus, in the prior art, the test vectors by which only one buffer is placed in the active state are selected after all possible test vectors are generated. However, as described above, it takes much time to generate all possible test vectors for the conventional data processing device. Further, the rate of the useful test vectors in all generated test vectors made by the CAT is lower reducing, the efficiency of the test vector generation.